Memory systems typically include a specified level of support for reliability, availability, and serviceability (RAS). The support for RAS may include support for detecting and/or correcting certain memory content errors. In addition, the support for RAS may include support for detecting and/or correcting certain signaling errors that generate faulty bits at the receiver.
The error detecting and/or correcting mechanisms typically involve adding redundant information to data to protect the data from specified faults. One example of an error detecting mechanism is a cyclic redundancy code (CRC). An example of an error correcting mechanism is an error correction code (ECC).
As processor speeds increase there is a corresponding pressure to increase the data rate supported by the memory bus. Typically, conventional memory buses are based on a multi-point (often referred to as a multi-drop) architecture. This conventional multi-point memory bus architecture is increasingly disfavored in light of the demand for significant increases in memory speed and size.
Point-to-point memory interconnects frequently support higher data rates than conventional memory buses. Point-to-point memory interconnects may use memory modules having buffers to isolate the memory interconnect from the memory devices on the module. Examples of point-to-point memory architectures include those based on fully-buffered dual inline memory module (DIMM) technology. Fully-buffered DIMM technology refers to a memory architecture that is based, at least in part, on any of the fully-buffered DIMM specifications promulgated by the Solid State Technology Organization (JEDEC). The higher data rates supported by point-to-point memory architectures, such as fully-buffered DIMM, present new challenges for providing an appropriate level of RAS.